To increase performance and reliability, multiprocessor systems typically rely on cache coherence architectures to provide a consistent view of data stored in the separate cache memories of electronic processing units of the system. Present-day standards of cache coherence architectures often use protocols that are designed based on an assumption of electronic processing unit symmetry, meaning that all of the processing units of a multiprocessor systems have homogenous computing characteristics such as similar clock speeds and bandwidths. Cache coherent protocols that are based on such a symmetry assumption apply the same caching protocol to all of the processing units. MOESI or MOI strategies, well known to those skilled in the pertinent art, are examples of symmetric cache coherent protocols. A general principle of such protocols is that data should be migrated to, and owned by, the memory cache of the processor that last used the data.
Problems can arise in the use of such symmetric cache coherent protocols for multiprocessor systems where the assumption of processor symmetry does not apply. For instance, a first processor having a high bandwidth (e.g., a data throughput), due to the ability to perform extensive parallel processing on different portions of data, can greatly slow down the computational speed of a second processor if the two processors are sharing some of the data according to a symmetric cache coherent protocol.